AMD Llano APU技術(shù)解析

今年初，AMD率先發(fā)布了低電壓版APU——E系列（研發(fā)代號(hào)：Zacate）和C系列（研發(fā)代號(hào)：Ontario）。雖然這兩款處理器發(fā)布之后的市場(chǎng)反響都比較不錯(cuò)，但是僅憑低電壓APU肯定是不能在市場(chǎng)中獲得更多的主動(dòng)權(quán)。因此，AMD在半年之后推出了代號(hào)為L(zhǎng)lano的A系列APU，很顯然AMD這次的矛頭直指英特爾的SandyBridge處理器。

眾所周知，“融合”概念最早是由AMD提出，而英特爾卻搶先于AMD推出了融合圖形芯片的處理器。雖然英特爾率先推出了整合顯卡的Core i5/i3處理器，不過(guò)，正如最初的Pentium D雙核處理器一樣，英特爾這種“CPU+GPU”的設(shè)計(jì)具有兩個(gè)獨(dú)立的芯片，僅僅是兩個(gè)功能模塊的簡(jiǎn)單疊加，屬于一種過(guò)渡方案，并非原生的單芯片解決方案。在臥薪嘗膽了兩年之后，AMD終于厚積薄發(fā)，推出了Llano的A系列APU。AMD的APU則是采用更先進(jìn)的原生方案——將CPU和GPU內(nèi)核完全融為一體的單芯片方案，這樣讓內(nèi)核之間的數(shù)據(jù)交換效率更高。

此次AMD一共發(fā)布了七款A(yù)PU，包括A4、A6和A8，從型號(hào)上來(lái)看，它們和英特爾的i3、i5和i7在數(shù)字上有著驚人的對(duì)稱(chēng)，不知道這是巧合還是AMD故意所為。和英特爾的SandyBridge處理器一樣，此次發(fā)布的所有AMD Llano A系列APU均配置了AMD HD6400以上系列顯示核芯，并且根據(jù)級(jí)別的不同，顯卡性能也有所區(qū)別。另外，最高級(jí)別的A8采用的是AMD Radeon HD 6620G，單從型號(hào)上來(lái)看，這款顯卡的性能應(yīng)該不低。

AMD LlanoAPU全系產(chǎn)品

Fusion APU主要由x86架構(gòu)的CPU核心（最先上市的Ontario和Zacate APU處理器將基于“Bobcat”架構(gòu)）、DirectX 11 SIMD引擎陣列、UVD高清視頻引擎、數(shù)據(jù)總線和DDR3內(nèi)存控制器等幾個(gè)模塊封裝在一個(gè)核心內(nèi)構(gòu)成。CPU和GPU各司其職，各自分別擁有獨(dú)立緩存。 CPU和GPU通過(guò)切換開(kāi)關(guān)互相連接，而整個(gè)APU內(nèi)部的各個(gè)組件之間通過(guò)HyperTransport總線連接成一個(gè)整體。CPU和GPU可以直接訪問(wèn) 存儲(chǔ)器，CPU和內(nèi)存之間，以及GPU和內(nèi)存之間均使用交叉開(kāi)關(guān)進(jìn)行連接，并且CPU和GPU可通過(guò)共享內(nèi)存進(jìn)行數(shù)據(jù)交換。APU這一設(shè)計(jì)的最大優(yōu)勢(shì)是可 以消除現(xiàn)有AMD平臺(tái)上各部分之間的互連瓶頸。在目前的AMD整合平臺(tái)上，原本位于北橋芯片的總線控制器和內(nèi)存控制器都已經(jīng)集成到CPU內(nèi)部，但是內(nèi)存控 制器與內(nèi)存之間的帶寬僅有17GB/s左右，北橋與集成顯卡之間的帶寬更是僅僅只有7GB/s左右，這已成為瓶頸所在。更為嚴(yán)重的是，集成顯卡與內(nèi)存通信 時(shí)還需要繞道北橋部分，增加了通信延時(shí)。AMD APU在將所有這些功能模塊全部整合到一塊晶片后，將可以提升各組件之間的帶寬。APU內(nèi)部的GPU圖形陣列、UVD解碼引擎與北橋模塊及內(nèi)存控制器之間 的通道高達(dá)27GB/s，內(nèi)存控制器和內(nèi)存之間的帶寬也同樣達(dá)到了27GB/s。另外，GPU與內(nèi)存之間也可以直接通信，帶寬增加了三倍，大大提高了GPU的執(zhí)行效率。

更強(qiáng)的整數(shù)運(yùn)算性能

盡管Fusion APU是一個(gè)全新的CPU和GPU的融合方案，GPU部分將采用與目前AMD Radeon HD 6300M/6250M相同級(jí)別的圖形核心，除了支持DirectX 11外，還能通過(guò)OpenCL支持GPU加速運(yùn)算。Fusion APU內(nèi)核架構(gòu)最大的亮點(diǎn)是引入了全新的“Bobcat”架構(gòu)。

Bobcat是AMD全新架構(gòu)的新一代處理器核心，與Bulldozer一樣，Bobcat也將整數(shù)運(yùn)算執(zhí)行單元和浮點(diǎn)單元分別獨(dú)立開(kāi)來(lái)，只不過(guò) Bobcat內(nèi)核的整數(shù)運(yùn)算“簇”比Bulldozer更少。

注：整數(shù)運(yùn)算“簇”

Bulldozer的內(nèi)核引入了靈活的模塊化設(shè)計(jì)：在現(xiàn)有的設(shè)計(jì)中，每個(gè)物理核心對(duì)應(yīng)單一獨(dú)占的整數(shù)運(yùn)算單元和128bit浮點(diǎn)運(yùn)算單元。而在 Bulldozer架構(gòu)中，每個(gè)物理核心具有兩個(gè)整數(shù)運(yùn)算單元和一個(gè)共享的256bit的浮點(diǎn)運(yùn)算單元。同時(shí)，這個(gè)256bit的浮點(diǎn)運(yùn)算單元可以根據(jù)需 要拆分為2個(gè)128bit的浮點(diǎn)運(yùn)算單元，供兩個(gè)整數(shù)運(yùn)算單元搭配使用；或是以1個(gè)256bit浮點(diǎn)運(yùn)算單元的模式供某個(gè)整數(shù)單元獨(dú)占。這樣一個(gè)單獨(dú)的單 元被AMD稱(chēng)為“核心模塊”，這也就是Bulldozer所謂“1.5核”說(shuō)法的由來(lái)。而當(dāng)多個(gè)Bulldozer處理器并聯(lián)時(shí)（這在服務(wù)器領(lǐng)域幾乎是必 然的），兩個(gè)“核心模塊”組成的“簇”便成為了AMD集群多線程技術(shù)中的基本單位。而B(niǎo)obcat處理核心中的“核心模塊”則只包含了一個(gè)整數(shù)單元和一個(gè) 浮點(diǎn)，并不支持集群多線程技術(shù)，故每?jī)蓚€(gè)核心模塊才只擁有一個(gè)“簇”單元。簡(jiǎn)單來(lái)說(shuō)，“簇”在這里被定義為整數(shù)計(jì)算能力，每?jī)蓚€(gè)整數(shù)單元等同于一個(gè) “簇”。

AMD為什么要在核心設(shè)計(jì)中單獨(dú)增加整數(shù)單元的數(shù)目？這與AMD的異構(gòu)計(jì)算策略不無(wú)關(guān)系。簡(jiǎn)單來(lái)說(shuō)，現(xiàn)有的GPU具有遠(yuǎn)遠(yuǎn)強(qiáng)于CPU的浮點(diǎn)計(jì)算能 力。在AMD提出的GPU與CPU協(xié)同計(jì)算的平臺(tái)戰(zhàn)略下，與其事倍功半地提升CPU的浮點(diǎn)計(jì)算能力，不如將浮點(diǎn)計(jì)算交與GPU完成。在這種情況下，整數(shù)計(jì) 算能力將成為制約整個(gè)平臺(tái)性能的瓶頸，那么，有意識(shí)地提升APU的整數(shù)計(jì)算能力無(wú)疑就是一種必然的選擇。

上圖左為Bobcat的一個(gè)“簇”，它的整數(shù)單元（INT）只相當(dāng)于Bulldozer（上圖右）的半個(gè)“簇”。

Fusion APU能否在移動(dòng)市場(chǎng)掀起波瀾

Bergman表示：“AMD A系列APU對(duì)于AMD而言具有拐點(diǎn)意義，它可能是自微處理器面世以來(lái)業(yè)界最大的架構(gòu)變革。此產(chǎn)品的推出將使筆記本和個(gè)人電腦擁有前所未有的圖形和視頻性能，將為用戶帶來(lái)全新計(jì)算體驗(yàn)。從今天開(kāi)始，我們將為廣大的主流用戶帶來(lái)獨(dú)顯性能。”

Fusion APU是一款真正將CPU和GPU融合在一起的產(chǎn)品，它的誕生將統(tǒng)治軟件業(yè)界的x86 CPU與針對(duì)現(xiàn)代負(fù)載進(jìn)行優(yōu)化的GPU緊密融合在一起，并將兩者各自的優(yōu)勢(shì)發(fā)揚(yáng)光大。尤其對(duì)于移動(dòng)平臺(tái)來(lái)說(shuō)，APU的利好是顯而易見(jiàn)的，高集成化可大幅度降低筆記本內(nèi)部設(shè)計(jì)的難度，并可有效提升其散熱效率，降低整機(jī)的功耗，提升續(xù)航時(shí)間。所以APU的出現(xiàn)將會(huì)帶出一種全新的筆記本內(nèi)部架構(gòu)，影響深遠(yuǎn)，符合更低能耗、更低成本的效果，符合節(jié)約、低碳、環(huán)保的時(shí)代主題。尤其在AMD將其定義為“APU價(jià)值和精華”的超輕薄筆記本電腦市場(chǎng)上，APU的問(wèn)世絕對(duì)是AMD的一枚重磅炸彈。最低低于1W的功耗設(shè)計(jì)，以及不到現(xiàn)今產(chǎn)品一半的核心面積實(shí)現(xiàn)90%的性能水平。

麥格理證券研究公司（Macquarie Equities Research）分析師Shawn Webster表示，通過(guò)新近發(fā)布的Llano和Bulldozer處理器，AMD將在桌面PC處理器市場(chǎng)贏得份額，除非英特爾采取降價(jià)措施。

AMD是否有機(jī)會(huì)在超輕薄市場(chǎng)逐步建立起自己的非對(duì)稱(chēng)優(yōu)勢(shì)，并最終在其他市場(chǎng)上對(duì)英特爾形成挑戰(zhàn)？業(yè)界將拭目以待。

------來(lái)源：EET

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附原文：

AMD makes Fusion CPU， GPU agnostic

Peter Clarke

Microprocessor vendor Advanced Micro Devices Inc. has declared that Fusion， its flagship processor project whereby it has combined x86 and graphics processors， will be CPU and GPU agnostic. The announcement was made as part of a keynote at the Fusion Developers Summit， being held in Bellevue， Washington， by Phil Rogers， AMD Corporate Fellow.

The early examples of Fusion have been based on x86 processor and GPU cores developed internally by AMD. However， AMD is clearly heading for a higher level of abstraction and believes it can do better by letting multiple hardware and software companies join with it as it tries to enable heterogeneous computing. It is effectively turning the Fusion marketing brand into the open Fusion System Architecture with a specification that enables chipmakers to combine multiple CPUs and GPUs and preserve an efficient programming model.

The development is likely to allow ARM cores to be used as part of the Fusion architecture although Rogers did not mention ARM explicitly as he laid out the open-platform plan for Fusion.

The main thrust of Roger‘s keynote was that AMD wants to create an architecture whereby different combinations of CPU and GPU processor cores operate as a unified processing engine that delivers both higher performance and lower power consumption compared with today’s variants.

Having discussed the historical trends from single- to multicore and on to heterogeneous multicore computing it was about half-way through the talk that Rogers described the Fusion System Architecture as an “open platform” and added that this meant the virtual ISA specification， known as FSAIL， the memory model the despatch mechanism would be published.

Rogers said： “The Fusion system architecture is ISA agnostic for both CPUs and GPUs. This is very important because we‘re inviting partners to join us in all areas; other hardware companies to implement FSA and join in the platform; operating systems companies to fully embrace all of the features and deliver its full performance and quality of service; tools and middleware companies to provide the tool infrastructure to develop， optimize and debug the programs that will run on this platform.”

He added that an FSA review committee would be formed to guide the evolution of the architecture and to allow all participants a voice in its direction.

unified memory and programming models

Rogers said that current heterogeneous multicore architectures are currently constrained by the programming model and communications overheads. “The good news is the Fusion System Architecture blows away both of these constraints，” he said. “Where we’re headed is the architected era. We make the GPU into a peer processor rather than a device，” he said

Rogers outlined a roadmap that includes support for C++ features， unification of the address space， support for nested data parallelism， user-mode scheduling for lower latency task dispatch between CPUs and GPUs， and the addition of pre-emption and context switching.

Automated lower balancing between CPU and GPU is part of that progress， according to Rogers. In addition， specific FSA enhancements will be supported by newer programming languages and interfaces such as OpenCL and DirectCompute. One of the next steps will be the addition of bi-directional power management to CPU， GPU combinations. But the key is the creation of a unified memory address space and fully coherent memory shared by the CPU and GPU so they operate seamlessly together， Rogers said.

What was not made clear in what was essentially a technical presentation is how AMD， as one of a number of implementors and contributors to the Fusion System Architecture will make its money from the development of Fusion.

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來(lái)源：[db:出處]

作者：tee