Virtex-6 FPGA適合用有線通信,無線基礎(chǔ)設(shè)備和廣播設(shè)備等領(lǐng)域.本文介紹了Virtex-6 FPGA主要特性,以及骨干網(wǎng)OTU-4成幀與EFEC框圖, LTE 2x2無線電設(shè)計框圖和支持SD/HD/3G-SDI接口的新一代交換框圖, Virtex®-6 FPGA ML605評估套件主要特性和詳細(xì)電路圖.

The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL™ (Advanced Silicon Modular Block) columnbased architecture, the Virtex-6 family contains multiple distinct sub-families. This overview covers the devices in the LXT, SXT, and HXT sub-families. Each sub-family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-in system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 40 nm state-of-theart copper process technology, Virtex-6 FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.

Virtex-6 FPGA 主要特性:

• Three sub-families:

• Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity

• Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity

• Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity

• Compatibility across sub-families

• LXT and SXT devices are footprint compatible in the same package

• Advanced, high-performance FPGA Logic

• Real 6-input look-up table (LUT) technology

• Dual LUT5 (5-input LUT) option

• LUT/dual flip-flop pair for applications requiring rich register mix

• Improved routing efficiency

• 64-bit (or two 32-bit) distributed LUT RAM option per 6-input LUT

• SRL32/dual SRL16 with registered outputs option

• Powerful mixed-mode clock managers (MMCM)

• MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division

• 36-Kb block RAM/FIFOs

• Dual-port RAM blocks

• Programmable

- Dual-port widths up to 36 bits

- Simple dual-port widths up to 72 bits

• Enhanced programmable FIFO logic

• Built-in optional error-correction circuitry

• Optionally use each block as two independent 18 Kb blocks

• High-performance parallel SelectIO™ technology

• 1.2 to 2.5V I/O operation

• Source-synchronous interfacing using ChipSync™ technology

• Digitally controlled impedance (DCI) active termination

• Flexible fine-grained I/O banking

• High-speed memory interface support with integrated write-leveling capability

• Advanced DSP48E1 slices

• 25 x 18, two’s complement multiplier/accumulator

• Optional pipelining

• New optional pre-adder to assist filtering applications

• Optional bitwise logic functionality

• Dedicated cascade connections

• Flexible configuration options

• SPI and Parallel Flash interface

• Multi-bitstream support with dedicated fallback reconfiguration logic

• Automatic bus width detection

• System Monitor capability on all devices

• On-chip/off-chip thermal and supply voltage monitoring

• JTAG access to all monitored quantities

• Integrated interface blocks for PCI Express® designs

• Compliant to the PCI Express Base Specification 2.0

• Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with GTX transceivers

• Endpoint and Root Port capable

• x1, x2, x4, or x8 lane support per block

• GTX transceivers: up to 6.6 Gb/s

• Data rates below 480 Mb/s supported by oversampling in FPGA logic.

• GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s

• Integrated 10/100/1000 Mb/s Ethernet MAC block

• Supports 1000BASE-X PCS/PMA and SGMII using GTX transceivers

• Supports MII, GMII, and RGMII using SelectIO technology resources

• 2500Mb/s support available

• 40 nm copper CMOS process technology

• 1.0V core voltage (-1, -2, -3 speed grades only)

• Lower-power 0.9V core voltage option (-1L speed grade only)

• High signal-integrity flip-chip packaging available in standard or Pb-free package options

Virtex®-6 FPGA典型應(yīng)用:


圖1.骨干網(wǎng)OTU-4成幀和EFEC框圖(有線通信)

圖2. LTE 2x2無線電設(shè)計框圖(無線基礎(chǔ)設(shè)備)

圖3.支持SD/HD/3G-SDI接口的新一代交換框圖(廣播通信)
[!--empirenews.page--]
Virtex®-6 FPGA ML605評估套件

The Virtex®-6 FPGA ML605 Evaluation Kit provides a development environment for system designs that demand high-performance, serial connectivity and advanced memory interfacing. The ML605 is supported by pre-verified reference designs and industry-standard FPGA Mezzanine Connectors (FMC) which allow scaling and customization with daughter cards. Integrated tools help streamline the creation of elegant solutions to complex design requirements.

The ML605 board enables hardware and software developers to create or evaluate designs targeting the Virtex®-6 XC6VLX240T-1FFG1156 FPGA.

The ML605 provides board features common to many embedded processing systems. Some commonly used features include: a DDR3 SODIMM memory, an 8-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O, and a UART.  Additional user desired features can be added through mezzanine cards attached to the onboard high-speed VITA-57 FPGA Mezzanine Connector (FMC) high pin count (HPC) expansion connector, or the onboard VITA-57 FMC low pin count (LPC) connector.

This information includes:

• Current version of this user guide in PDF format

• Example design files for demonstration of Virtex-6 FPGA features and technology

• Demonstration hardware and software configuration files for the System ACE™ CF controller, Platform Flash configuration storage device, and linear flash chip

• Reference design files

• Schematics in PDF and DxDesigner formats

• Bill of materials (BOM)

• Printed-circuit board (PCB) layout in Allegro PCB format

• Gerber files for the PCB (Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files.)

• Additional documentation, errata, frequently asked questions, and the latest news

Virtex®-6 FPGA ML605評估套件主要特性:

The ML605 provides the following features:

• 1. Virtex-6 XC6VLX240T-1FFG1156 FPGA

• 2. 512 MB DDR3 Memory SODIMM

• 3. 128 Mb Platform Flash XL

• 4. 32 MB Linear BPI Flash

• 5. System ACE CF and CompactFlash Connector

• 6. USB JTAG

• 7. Clock Generation

♦ Fixed 200 MHz oscillator (differential)

♦ Socketed 2.5V oscillator (single-ended)

♦ SMA connectors (differential)

♦ SMA connectors for MGT clocking

• 8. Multi-Gigabit Transceivers (GTX MGTs)

♦ FMC - HPC connector

♦ FMC - LPC connector

♦ SMA

♦ PCIe

♦ SFP Module connector

♦ Ethernet PHY SGMII interface

• 9. PCI Express Endpoint Connectivity

♦ Gen1 8-lane (x8)

♦ Gen2 4-lane (x4)

• 10. SFP Module Connector

• 11. 10/100/1000 Tri-Speed Ethernet PHY

• 12. USB-to-UART Bridge

• 13. USB Controller

• 14. DVI Codec

• 15. IIC Bus

♦ IIC EEPROM - 1 KB

♦ DDR3 SODIMM socket

♦ DVI CODEC

♦ DVI connector

♦ FMC HPC connector

♦ FMC LPC connector

♦ SFP module connector


圖4.ML605和外設(shè)框圖

圖5.ML605板外形圖[!--empirenews.page--]

圖6.ML605電路圖(1)

圖7.ML605電路圖(2)

圖8.ML605電路圖(3)

圖9.ML605電路圖(4)

圖10.ML605電路圖(5)

圖11.ML605電路圖(6)

圖12.ML605電路圖(7)

圖13.ML605電路圖(8)

圖14.ML605電路圖(9)

圖15.ML605電路圖(10)